Design for Test and Debug Engineer Graduate Intern
Posted on: May 26, 2023
Come intern with the Programmable Solutions Group to work on exciting on FPGAs and Structured ASIC designs. You get to work on Design for test and design for debug on innovative designs.
Your responsibilities will allow you to drive technical issues, debug and resolution involving silicon, software, hardware, and firmware through interface with cross-functional teams with respect to testing methods, procedures, device specification issues, and test-related optimization.
Length of the internship: 3 months with the possibility to extend per business needs up to 12 months.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Pursing a Master's or PhD degree in Electrical Engineering or related field.
Must have experience or coursework in Behavioral RTL coding, such as Verilog, System Verilog etc.
Prefer the candidate to have experience or coursework working with EDA (Electronic Design Automation) tools for IC design, validation, DFT (Design for Test) etc.
Prefer experience or coursework with Validation/verification of digital/analog circuits.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Keywords: Intel, Charleston , Design for Test and Debug Engineer Graduate Intern, Engineering , Charleston, West Virginia
here to apply!